About

Zach Sisco is a CCS Computing Fellow at the UCSB College of Creative Studies. His affiliation indicates a focus on computing within the college's interdisciplinary environment. The available information does not specify his research interests, background, or key contributions beyond his role as a fellow and his contact details. No additional biographical details are provided on the page.

Research topics

• Computer Science
• Computer hardware
• Embedded system
• Operating system
• Computer architecture
• Programming language
• Parallel computing
• Philosophy
• History

Selected publications

• Register Aggregation for Hardware Decompilation

  arXiv (Cornell University) · 2024

  Senior authorCorresponding
  • Computer Science
  • Computer Science
  • Computer hardware

  Hardware decompilation reverses logic synthesis, converting a gate-level digital electronic design, or netlist, back up to hardware description language (HDL) code. Existing techniques decompile data-oriented features in netlists, like loops and modules, but struggle with sequential logic. In particular, they cannot decompile memory elements, which pose difficulty due to their deconstruction into individual bits and the feedback loops they form in the netlist. Recovering multi-bit registers and memory blocks from netlists would expand the applications of hardware decompilation, notably towards retargeting technologies (e.g. FPGAs to ASICs) and decompiling processor memories. We devise a method for register aggregation, to identify relationships between the data flip-flops in a netlist and group them into registers and memory blocks, resulting in HDL code that instantiates these memory elements. We aggregate flip-flops by identifying common enable pins, and derive the bit-order of the resulting registers using functional dependencies. This scales similarly to memory blocks, where we repeat the algorithm in the second dimension with special attention to the read, write, and address ports of each memory block. We evaluate our technique over a dataset of 13 gate-level netlists, comprising circuits from binary multipliers to CPUs, and we compare the quantity and widths of recovered registers and memory blocks with the original source code. The technique successfully recovers memory elements in all of the tested circuits, even aggregating beyond the source code expectation. In 10 / 13 circuits, all source code memory elements are accounted for, and we are able to compact up to 2048 disjoint bits into a single memory block.

  PublisherOA PDFDOI

• There and Back Again: A Netlist's Tale with Much Egraphin'

  arXiv (Cornell University) · 2024

  • Computer Science
  • Computer Science
  • History

  EDA toolchains are notoriously unpredictable, incomplete, and error-prone; the generally-accepted remedy has been to re-imagine EDA tasks as compilation problems. However, any compiler framework we apply must be prepared to handle the wide range of EDA tasks, including not only compilation tasks like technology mapping and optimization (the "there"} in our title), but also decompilation tasks like loop rerolling (the "back again"). In this paper, we advocate for equality saturation -- a term rewriting framework -- as the framework of choice when building hardware toolchains. Through a series of case studies, we show how the needs of EDA tasks line up conspicuously well with the features equality saturation provides.

  PublisherOA PDFDOI

• Control Logic Synthesis: Drawing the Rest of the OWL

  2024-04-27 · 2 citations

  articleOpen access1st authorCorresponding

  System-on-chip (SoC) design requires complex reasoning about the interactions between an architectural specification, the microarchitectural datapath (e.g., functional units), and the control logic (which coordinates the datapath) to facilitate the critical computing tasks on which we all depend. Hardware specialization is now the expectation rather than the exception, meaning we need new hardware design tools to bring ideas to reality with both agility and correctness.

  PublisherOA PDFDOI

• Loop Rerolling for Hardware Decompilation

  Proceedings of the ACM on Programming Languages · 2023 · 9 citations

  1st authorCorresponding
  • Computer Science
  • Computer Science
  • Programming language

  We introduce the new problem of hardware decompilation . Analogous to software decompilation, hardware decompilation is about analyzing a low-level artifact—in this case a netlist , i.e., a graph of wires and logical gates representing a digital circuit—in order to recover higher-level programming abstractions, and using those abstractions to generate code written in a hardware description language (HDL). The overall problem of hardware decompilation requires a number of pieces. In this paper we focus on one specific piece of the puzzle: a technique we call hardware loop rerolling . Hardware loop rerolling leverages clone detection and program synthesis techniques to identify repeated logic in netlists (such as would be synthesized from loops in the original HDL code) and reroll them into syntactic loops in the recovered HDL code. We evaluate hardware loop rerolling for hardware decompilation over a set of hardware design benchmarks written in the PyRTL HDL and industry standard SystemVerilog. Our implementation identifies and rerolls loops in 52 out of 53 of the netlists in our benchmark suite, and we show three examples of how hardware decompilation can provide concrete benefits: transpilation between HDLs, faster simulation times over netlists (with mean speedup of 6x), and artifact compaction (39% smaller on average).

  PublisherOA PDFDOI

• Verifying Data-Oriented Gadgets in Binary Programs to Build Data-Only Exploits

  Journal of Bioresource Management · 2018-01-01

  articleOpen access1st authorCorresponding

  Verifying Data-Oriented Gadgets in Binary Programs to Build Data-Only Exploits

  PublisherOA PDF

• Modeling information flow for an autonomous agent to support reverse engineering work

  The Journal of Defense Modeling and Simulation Applications Methodology Technology · 2016-10-11 · 3 citations

  article1st authorCorresponding

  Reverse engineering is a cyber defense task used to investigate malware, reconstruct functionality of compiled software, and identify vulnerabilities from closed-source software code already being used in operational contexts. While research in this area has mainly focused on techniques to extract information from binary code, it is also important to understand the capabilities and limitations of the human involved in the reverse engineering process (both defensively and offensively), so we can design better information representations and effectively allocate appropriate tasks to autonomous agents. In this paper, we describe our introductory work in developing agent models of reverse engineering. We review what is known about reverse engineers’ mental models, then describe and characterize four human–computer interaction patterns involved in reverse engineering from a cognitive task analysis. Finally, we present a category theoretic model to describe how reverse engineers trace information flow when performing static analysis. Our approach is a first step in modeling, simulating, and optimizing the human interaction components of these tasks to increase the speed, scale, and accuracy of cyber defense efforts.

  PublisherDOI

Frequent coauthors

• Jonathan Balkind

  University of California, Santa Barbara

  2 shared

• Zachary Tatlock

  University of Washington

  1 shared

• Jingtao Xia

  1 shared

• Vishal Canumalla

  Seattle University

  1 shared

• Ben Hardekopf

  University of California, Santa Barbara

  1 shared

• Patrick P. Dudenhofer

  1 shared

• Gus Henry Smith

  1 shared

• Adam R. Bryant

  1 shared

Education

• PhD, Computer Science

  University of California, Santa Barbara

  2025