About

Yong-Bin Kim is a Professor in the Department of Electrical and Computer Engineering at Northeastern University. He was born in Seoul, South Korea, and received his B.S. degree in Electronic Engineering from Sogang University in Seoul. He earned his M.S. degree in Computer Engineering from the New Jersey Institute of Technology and his Ph.D. in Computer Engineering from Colorado State University. His professional experience includes positions at the Electronics and Telecommunications Research Institute in South Korea, Intel Corporation, Hewlett Packard Co., and Sun Microsystems, where he contributed to microprocessor chip design. He served as an assistant professor at the University of Utah before joining Northeastern University in 2000. His research focuses on high-speed low-power VLSI circuit design and methodology, including integrated circuit design for nanoelectronics and nanotechnology, high-speed system integration for signal processing and communication, bio-chip and bio-sensor interface circuit design, electronic neuron circuit design, and low-power adaptive robot controller circuit design. He has been recognized with awards such as the Outstanding Paper Award at the 2020 IEEE ISOCC conference and holds patents related to impedance calibration and receiver circuits for semiconductor devices.

Research topics

• Computer Science
• Engineering
• Mathematics
• Electronic engineering
• Artificial Intelligence
• Algorithm
• Electrical engineering
• Parallel computing
• Operating system
• Embedded system
• Arithmetic
• Physics
• Computer engineering
• Materials science
• Computer hardware

Selected publications

• Performance Evaluation of Adaptive Stochastic Computing Based Image Processing Approaches

  2025-10-12

  article

  Recent advancements in approximate stochastic computing (ASC) have shown substantial potential in addressing the challenges of high-speed and energy-efficient computation, especially in resource and power constrained environment. ASC operates on the principle of compromising a limited degree of computational accuracy to achieve significant gains in performance metrics such as power consumption, area efficiency, and processing speed. This trade-off is particularly beneficial in emerging domains such as machine learning, artificial intelligence, signal processing, and image analysis, where exact numerical precision is often unnecessary, and near-optimal results are sufficient for practical applications. Among various image processing techniques, edge detection plays a fundamental role in object recognition, segmentation, and scene understanding. The Roberts-Cross operator, a classical method for gradient-based edge detection, is known to be suitable for lightweight implementations due to its computational simplicity. In this paper, we present a time- and area-efficient ASC-based design for implementing the Roberts-Cross edge detection algorithm. We explore the design's architectural characteristics and assess its effectiveness through detailed performance evaluation metrics, including accuracy, power consumption, resource utilization, and output fidelity. Our results demonstrate the viability of ASC as a compelling approach for low-power, high-throughput image processing applications.

  PublisherDOI

• A Novel Area Efficient Approximate Stochastic Computing Approach for Edge Devices

  2024-08-19 · 1 citations

  article

  Recent advancements in approximate stochastic computing (ASC) hold great promise for achieving fast and energy-efficient computation in low-power edge devices utilizing system-on-chip (SoC) technology. ASC is particularly relevant in machine learning, AI and image processing applications, where the overall precision of computation can be intentionally reduced for fast and low-power approximate computation. This reduction in precision allows us to meet design constraints and performance requirements while still obtaining acceptable results. In this paper, we propose a novel area-efficient approach for stochastic approximate computing circuits and compare it with the existing approach in terms of truncation error.

  PublisherDOI

• Low-Power Counters using Pathfinding Technique

  2023-10-25

  articleSenior author

  This paper proposed a novel pathfinding method to implement low-power binary counters. It performs unique data shifting in custom designed pathfinding array to generate output. The pathfinding counters are built in Cadence Virtuoso using Samsung $65 \mathrm{~nm}$ technology with $1 \mathrm{~V}$ supply. The simulation results show better power efficiency compared to other digital counters. The 7:3 counter spends only $6.1 \mu \mathrm{W}$ power with $2.26 \mathrm{~ns} \cdot \mu \mathrm{W}$ PDP. And $15: 4$ pathfinding counter dissipates $20 \mu \mathrm{W}$ and has $12.8 \mathrm{~ns} \cdot \mu \mathrm{W}$ PDP. The pathfinding counter has great potential be implemented in neural engines to achieve superb power and area efficiency.

  PublisherDOI

• Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits

  2023-10-25 · 1 citations

  article

  Developments in approximate stochastic computing (ASC) are promising for fast and low-power computing in edge devices based on SoC technology. ASC is anticipated to be useful in machine learning and image processing applications where overall precision of computation can be lowered by truncation of low-order bits in bitstreams to achieve acceptable results just enough to meet the design constraints and performance requirements. In this paper, we propose a quantitative approach to evaluate the approximation error of stochastic computing circuits so the optimal compromise between precision and performance can be achieved.

  PublisherDOI

• A Time-Domain Parallel Counter for Deep Learning Macro

  2022 19th International SoC Design Conference (ISOCC) · 2022-10-19

  articleSenior author

  This paper proposes a novel time-domain parallel counter that can handle large number of input bits with good power efficiency and fast speed. This new design turns parallel counting into time-domain accumulation by using two-value delay unit. The circuit is implemented with 63-bit input scheme and simulated using a 65nm CMOS technology with 1V power supply. The results show that the new architecture's speed and power increase linearly with the number of input bits which shows great potential in deep learning implementation where large-number accumulation is needed.

  PublisherDOI

• Time-Efficient Approximate Stochastic Computing for Medical Imaging Applications

  2022 19th International SoC Design Conference (ISOCC) · 2022-10-19 · 4 citations

  article

  Recent advances in approximate stochastic computing (ASC) exploit the benefits of approximation for reduced HW/SW complexities where fast and power-efficient computing with relaxed precision and accuracy are desired such as image processing, machine learning and AI. A novel time-efficient approximation method improving ASC is proposed and its performance is compared and verified in this work. The proposed method has been modeled in Matlab to compare against the state-of-the-art ASC approach and is shown to perform better than previous approaches for portable medical image processing applications.

  PublisherDOI

• FPGA-based Scalable Road Image Stochastic Denosing Approach

  2021-10-06 · 1 citations

  article

  This work proposes FPGA-based stochastic computing for efficient and scalable road image stochastic denoising. Stochastic number generators were compared for fields requiring data reliability such as automotive vehicles. The denoising performance of PRNG (Pseudo-Random Number Generator) and LDSG (Low Discrepancy Sequence Generator) are showed in noised KETTI dataset with filtering algorithms. The proposed approach is expected to be easily applied to SoCs with embedded FPGA for lightweight embedded implementation of image denoising algorithms.

  PublisherDOI

• Stochastic Edge Detection for Fine-Grained Progressive Precision

  2022 19th International SoC Design Conference (ISOCC) · 2021 · 4 citations

  • Computer Science
  • Computer Science
  • Artificial Intelligence

  Stochastic Computing (SC) is a method of performing an operation by expressing a probability in a bitstream. This format is simpler than the format of conventional binary computing and can be implemented in hardware with fewer resources. In addition, by using a Low-Discrepancy (LD) sequence, faster convergence can be derived. This paper shows the experimental results of applying SC using LD sequence to edge detection algorithms including Sobel and Roberts Cross to analyze the progressive precision performance and scalability.

  PublisherDOI

• A Time-Domain Computing-In-Memory Micro using Ring Oscillator

  2022 19th International SoC Design Conference (ISOCC) · 2021 · 5 citations

  Senior authorCorresponding
  • Computer Science
  • Computer Science
  • Parallel computing

  This paper proposes a novel time-domain computing-in-memory core that implements XNOR-and-accumulate (XAC) of XNOR network in 8T SRAM cell. This new technique uses an inverter-based ring oscillator to generate periodic waves whose period represents the accumulation result of the input XNOR values. The circuit is built and simulated using PTM16_HP 16nm CMOS model with a 0.7V power supply. The results show correct functionality, a large signal margin and 463 TOPS/W efficiency. With further exploration, the time-domain computation could be a new candidate for in-memory computing since it has its own superiorities in comparison to mixed-signal or digital methods.

  PublisherDOI

• A Stray-Insensitive Low-Power Capacitive Sensor Interface with Time-Compensation Technique

  2021-08-09 · 2 citations

  articleSenior author

  This paper proposes a low-power capacitive sensor interface using novel time-compensation technique to eliminate the effect of stray capacitance. The interface comprises a capacitance-to-current converter charging a load capacitor and a time-compensation control system. Even with large stray capacitance, the control system will adjust the charging time, thereby ensuring the same measurement. Besides, the system only requires a few switches and two comparators which makes this technique unique regarding simplicity, low-cost of power and chip area. To prove the idea, the circuit was designed and simulated using 0.18μm standard CMOS technology powered from ±1V supply. It accomplishes 125kHz measuring frequency, ±1pF capacitance variation, and a sensitivity of 0.5mV/fF with only 30μW average power consumption. The simulation also shows an accurate output result within 1% difference between 6pF parasitic capacitance and no parasitic.

  PublisherDOI

Frequent coauthors

• Minsu Choi

  Missouri University of Science and Technology

  46 shared

• Fabrizio Lombardi

  Northeastern University

  45 shared

• Kyung Ki Kim

  Daegu University

  40 shared

• In-Seok Jung

  LG (South Korea)

  17 shared

• Jun-Hyup Lee

  Yonsei University

  15 shared

• Yongmin Kim

  15 shared

• Minseok Kang

  Seoul National University

  15 shared

• Vigil Varghese

  Australian Centre for Robotic Vision

  15 shared

Education

• Ph.D, Electrical and Comouter Engineering

  Colorado State University

  1996

Awards & honors

• Outstanding Paper Award in 2020 IEEE ISOCC conference for th…
• South Korean Patent for Autonomous Impedance Calibration on…
• Patent for Improved Receiver Circuit that Recovers the Trans…
• Detecting Trojan Circuits with On-Chip Temperature Sensors P…
• Patent for Impedance calibration device for semiconductor de…