
Vijay Ganesh
Georgia Institute of Technology · Computer Science
Active 1999–2026
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About
Dr. Vijay Ganesh is a professor of computer science at the Georgia Institute of Technology. He serves as the Associate Director of the IDEaS Institute and is affiliated with Tech AI. Prior to joining Georgia Tech in 2023, Vijay was a professor at the University of Waterloo in Canada from 2012 to 2023 and a research scientist at the Massachusetts Institute of Technology from 2007 to 2012. He completed his PhD in computer science from Stanford University in 2007. Vijay's primary area of research is the theory and practice of SAT/SMT solvers, and their application in AI, software engineering, security, mathematics, and physics. He has led the development of many SAT/SMT solvers, most notably, STP, Z3str4, AlphaZ3, MapleSAT, and MathCheck. His research includes proving several decidability and complexity results in the context of first-order theories. Recently, he has focused on the intersection of learning and reasoning, particularly the use of machine learning for efficient solvers and developing solvers aimed at making AI more trustworthy, secure, and robust. Vijay has received over 30 awards, honors, and medals for his research, including an ACM Impact Paper Award at ISSTA 2019, an ACM Test of Time Award at CCS 2016, and a Ten-Year Most Influential Paper citation at DATE 2008.
Research topics
- Biology
- Genetics
- Computational biology
- Bioinformatics
Selected publications
Metagenomic sequencing with spiked primer enrichment for viral diagnostics and genomic surveillance
Nature Microbiology · 2020-01-13 · 196 citations
articleOpen accessBeyond the exome: What’s next in diagnostic testing for Mendelian conditions
The American Journal of Human Genetics · 2023 · 117 citations
Centers for Mendelian Genomics: A decade of facilitating gene discovery
Genetics in Medicine · 2022-02-08 · 80 citations
reviewOpen accessBtor2-Select: Machine Learning Based Algorithm Selection for Hardware Model Checking
Lecture notes in computer science · 2025-01-01 · 4 citations
book-chapterOpen accessSenior authorAbstract In recent years, a diverse variety of hardware model-checking tools and techniques that exhibit complementary strengths and distinct weaknesses have been proposed. This state of affairs naturally suggests the use of algorithm-selection techniques to select the right tool for a given instance. To automate this process, we present Btor2-Select , a machine learning-based algorithm-selection framework for the hardware model-checking problem described in the word-level modeling language Btor…
Algorithm Selection for Word-Level Hardware Model Checking (Student Abstract)
Proceedings of the AAAI Conference on Artificial Intelligence · 2025-04-11 · 2 citations
articleOpen accessSenior authorWe build the first machine-learning-based algorithm selection tool for hardware verification described in the Btor2 format. In addition to hardware verifiers, our tool also selects from a set of software verifiers to solve a given Btor2 instance, enabled by a Btor2-to-C translator. We propose two embeddings for a Btor2 instance, Bag of Keywords and Bit-Width Aggregation. Pairwise classifiers are applied for algorithm selection. Upon evaluation, our tool Btor2-Select solves 30.0% more instances a…
Frequent coauthors
- 209 shared
Anne O’Donnell‐Luria
Broad Institute
- 119 shared
Lynn Pais
- 106 shared
Daniel G. MacArthur
UNSW Sydney
- 104 shared
Ben Weisburd
Broad Institute
- 101 shared
Anne Piantadosi
Emory University
- 96 shared
Heidi L. Rehm
Massachusetts General Hospital
- 95 shared
Shibani S. Mukerji
Massachusetts General Hospital
- 92 shared
Isaac H. Solomon
Education
- 2000
MS, Electrical Engineering, Stanford University
Stanford University
- 1994
B-Tech, Electronics and Communications
College of Engineering Trivandrum
Awards & honors
- ACM Impact Paper Award at ISSTA 2019
- ACM Test of Time Award at CCS 2016
- Ten-Year Most Influential Paper citation at DATE 2008
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