About

Miriam Leeser is a Professor in Electrical and Computer Engineering at Northeastern University, where she is also the head of the Reconfigurable Computing Laboratory and a member of the Computer Engineering research group. Her research focuses on accelerators for computer-intensive applications from the edge to the cloud, including applications of FPGAs in wireless communications, machine learning, and data privacy. She is involved in developing tools, libraries, and interfaces to make hardware accelerators such as FPGAs and GPUs easier to use, thereby enhancing the performance of wireless networking, IoT, medical imaging, security, and privacy applications. Professor Leeser holds a PhD in Computer Science from Cambridge University and has been with Northeastern University since 1996. She is a senior member of both the IEEE and the ACM, and her work has contributed significantly to the advancement of reconfigurable and GPU computing. Her research includes developing frameworks and testbeds for next-generation cloud platforms, secure computation infrastructures, and wireless communication systems, with a focus on practical implementation and speedup of algorithms. She has received numerous honors and awards, including being a charter member of the IEEE Computer Society Distinguished Contributor Program and a Fulbright Scholar.

Research topics

• Computer Science
• Artificial Intelligence
• Computer engineering
• Computer hardware
• Operating system
• Algorithm
• Embedded system
• Parallel computing
• Engineering
• Electrical engineering
• Distributed computing
• Computer architecture
• Software engineering
• World Wide Web

Selected publications

• Artifact Evaluation in the FPGA Community and in ACM TRETS

  ACM Transactions on Reconfigurable Technology and Systems · 2026-03-14

  articleOpen access1st authorCorresponding

  Artifact evaluation (AE) is gaining traction across the computer science community as a means of advancing reproducible research and strengthening readers’ confidence in published results. Applying reproducibility to computer systems and architecture research has proven particularly challenging, and the FPGA community faces its own distinct hurdles—namely, the use of non-standard hardware platforms and dependence on specific software tools and versions. In this editorial, we review the history of AE in the FPGA community, compare it to practices in related fields, and discuss challenges and future directions. To date, AE has meaningfully improved the availability and accessibility of artifacts and their documentation, while also increasing readers’ confidence in published findings. Looking ahead, AE is poised to continue growing across the reconfigurable hardware community. Notably, ACM Transactions on Reconfigurable Technology and Systems will now offer AE with the opportunity to earn artifact badges for all accepted papers.

  PublisherDOI

• High-AccuracyPolynomial Model Training for RF Power Amplifiers: Leveraging FISTA Unrolling

  IEEE Microwave and Wireless Technology Letters · 2026-01-01

  articleOpen accessSenior author

  Power amplifier (PA) behavioral modeling, incorporating nonlinearity and memory effects, provides the basis for predistorters and accurate base station models for analyzing cellular network coverage. In this letter, we present two fast iterative shrinkage and thresholding algorithm (FISTA) approaches to PA behavioral modeling: an FISTA-based and a learnable FISTA-based method for parameter estimation of a polynomial model. FISTA addresses sparsity-regularized linear inverse problems with low complexity and fast convergence, enabling the efficient feature selection in PA modeling. Both approaches are experimentally validated using a 100-MHz bandwidth signal. The proposed coefficient extraction techniques demonstrate superior accuracy and speed while maintaining the computational efficiency compared with commonly used models like the memory polynomial (MP), generalized MP (GMP), and popular neural network (NN) models.

  PublisherDOI

• Computationally Efficient Flexible Estimation with Elastic Net for Digital Predistortion

  2026-01-18

  articleSenior author

  This research investigates Elastic Net and demonstrates its effectiveness as a regularization technique for digital predistortion (DPD). Elastic Net is compared to the popular and recent techniques including a standard Least Squares (LS) approach, Ridge Regression, and Least Absolute Shrinkage and Selection Operator (LASSO). Performance of these regularization techniques is compared using adjacent channel power ratio (ACPR), normalized mean square error (NMSE), and number of coefficients. Elastic Net consistently performed better compared to linearization with other regularization methods and achieved over 3dB better NMSE and ACPR performance on average. An experimental hardware testbed with multiple Doherty power amplifiers was used to validate the use of Elastic Net for DPD.

  PublisherDOI

• TerraSense: FPGA Accelerated Vision-based Terrain Classification for Autonomous Robot Navigation

  2025-12-02

  articleSenior author
  PublisherDOI

• LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference

  2025-01-20 · 4 citations

  articleOpen access

  For FPGA-based neural network accelerators, digital signal processing (DSP) blocks have traditionally been the cornerstone for handling multiplications. This paper introduces LUTMUL, which harnesses the potential of look-up tables (LUTs) for performing multiplications. The availability of LUTs typically outnumbers that of DSPs by a factor of 100, offering a significant computational advantage. By exploiting this advantage of LUTs, our method demonstrates a potential boost in the performance of FPGA-based neural network accelerators with a reconfigurable dataflow architecture. Our approach challenges the conventional peak performance on DSP-based accelerators and sets a new benchmark for efficient neural network inference on FPGAs. Experimental results demonstrate that our design achieves the best inference speed among all FPGA-based accelerators, achieving a throughput of 1627 images per second and maintaining a top-1 accuracy of 70.95% on the ImageNet dataset.

  PublisherOA PDFDOI

• Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs

  ArXiv.org · 2025-04-23

  preprintOpen accessSenior author

  Sketch-based algorithms for network traffic monitoring have drawn increasing interest in recent years due to their sub-linear memory efficiency and high accuracy. As the volume of network traffic grows, software-based sketch implementations cannot match the throughput of the incoming network flows. FPGA-based hardware sketch has shown better performance compared to software running on a CPU when handling these packets. Among the various sketch algorithms, Count-min sketch is one of the most popular and efficient. However, due to the limited amount of on-chip memory, the FPGA-based count-Min sketch accelerator suffers from performance drops as network traffic grows. In this work, we propose a hardware-friendly architecture with a variable width memory counter for count-min sketch. Our architecture provides a more compact design to store the sketch data structure effectively, allowing us to support larger hash tables and reduce overestimation errors. The design makes use of a P4-based programmable data plane and the AMD OpenNIC shell. The design is implemented and verified on the Open Cloud Testbed running on AMD Alveo U280s and can keep up with the 100 Gbit link speed.

  PublisherOA PDFDOI

• A Survey of FPGA-based 3D CNN Accelerators and Hardware-aware Algorithmic Optimizations

  ACM Computing Surveys · 2025-11-18 · 2 citations

  articleOpen accessSenior author

  3D Convolutional Neural Networks (3D CNNs) can outperform 2D CNNs on several tasks, including action recognition, video captioning, abnormal event detection, and medical image interpretation. Compared to 2D CNNs, 3D CNNs have a larger number of parameters and higher computational complexity. For this reason, researchers have focused on designing efficient 3D CNN architectures and hardware accelerators. The purpose of this survey is to serve as a guide to recent work on 3D CNNs for action recognition with a focus on FPGA-based accelerators and hardware-aware algorithmic optimizations. We provide an overview of the state-of-the-art in 3D CNN architectures as well as the action recognition datasets used for training and testing the architectures. A performance comparison of 2D versus 3D CNNs on two datasets (Sports-1M and UCF101) is included. We explore the designs of FPGA-based accelerators and compare them in terms of achieved throughput, resource utilization, and power. We survey current methods of optimization for 3D CNN architectures, which are meant to reduce the number of parameters and the memory requirements and to facilitate their deployment on FPGAs. Finally, we highlight current challenges and potential areas of improvement in acceleration of 3D CNNs on FPGA platforms.

  PublisherDOI

• A design and simulation methodology for radio frequency receiver front-ends with frequency selective limiting devices

  Analog Integrated Circuits and Signal Processing · 2025-10-09

  articleOpen access

  Abstract It has recently been shown that emerging frequency selective limiter (FSL) devices allow to suppress interference with high power levels in the same frequency band as desired signals. This paper introduces an FSL model for circuit simulations that was validated with measurement results of a prototype FSL device. An RF front-end was constructed with this FSL model and a transistor-level CMOS low-noise amplifier (LNA) design. A co-simulation methodology has been developed under large-signal interference considerations using the Bluetooth Low-Energy (BLE) standard as a representative example. Results from simulations with a two-tone signal confirm that the modeled FSL can provide a 9.4 dB reduction of the third-order intermodulation distortion (IMD3) components, which benefits resilience to interference.

  PublisherOA PDFDOI

• Robust Digital Pre-Distortion Parameter Estimation with Interpretable Feature Selection

  2025-01-19 · 1 citations

  article

  Batch estimation using Least Squares (LS) is commonly used to calculate DPD coefficients. However, non-orthogonal polynomial-based structures in DPD lead to multicollinearity, causing ill conditioning in coefficient calculation. This paper introduces an improved Ridge Regression technique for digital pre-distortion (DPD) parameter reduction. Using Ridge Leverage, we identify DPD basis functions with minimal impact on linearization performance, achieving a 39% reduction in DPD coefficients.

  PublisherDOI

• Transfer Learning on the Edge for a Wireless Application Using an SoC Platform

  2025-05-04

  articleSenior author

  Edge devices with limited resources are critical components of modern wireless communication systems. As communication environments become increasingly complex, neural networks are playing a larger role in processing large amounts of data to enable Machine Learning (ML) within these systems. While most FPGA-based accelerators focus on neural network inference, deploying the training phase on resource-constrained edge devices remains a significant challenge. Training on a System on Chip (SoC) that combines ARM processors with FPGA fabric provides unique benefits, including the ability to quickly adapt models to dynamic environments. This work leverages the Tiny Transfer Learning (TinyTL) framework for on-device training, which allows edge devices to continuously adapt neural network models to new data with minimal memory requirements. To the best of our knowledge, this is the first use of a heterogeneous platform to accelerate training using TinyTL. We present the Accelerating TinyTL-based Digital PreDistortion (ATDPD) system, designed to adapt to varying behaviors of power amplifiers in wireless communication systems and implement it on an AMD RFSoC. Our heterogeneous approach achieves comparable training accuracy to ARM-based systems, while accelerating the training phase by more than 20%.

  PublisherDOI

Recent grants

• ICE-T: RI: Software Hardware Efficient Extensible Protocols (SHEEP)

  NSF · $100k · 2018–2020

• EAGER: Collaborative Research: CNS: PRATE: P4 Research enabled by Accelerators in national TestbEds

  NSF · $180k · 2021–2023

Frequent coauthors

• Novella Bartolini

  Sapienza University of Rome

  64 shared

• Domenico Garlisi

  University of Palermo

  64 shared

• Mariam Kiran

  64 shared

• Lisandro Zambenedetti Granville

  Universidade Federal do Rio Grande do Sul

  64 shared

• R. Dutta

  Sapienza University of Rome

  64 shared

• Ezra Kissel

  Lawrence Berkeley National Laboratory

  64 shared

• Johann Marquez

  Sapienza University of Rome

  64 shared

• Eiji Kawai

  Sapienza University of Rome

  64 shared

Education

• PhD, Computing Laboratory

  University of Cambridge

  1988

• Diploma, Computer Laboratory

  University of Cambridge

  1984

• BS, Electrical Engineering

  Cornell University

  1980

Awards & honors

• charter member of the IEEE Computer Society Distinguished Co…
• Fulbright Scholar
• National Science Foundation Young Investigator Award
• CNERT Workshop Best Paper Award