About

Professor Lionel C. Kimerling is the Thomas Lord Professor in Materials Science and Engineering at MIT. His research centers on the design and processing of semiconductor materials and devices, with a fundamental impact on understanding the chemical and electrical properties of defects in semiconductors. His work has enabled the development of long-lasting telecommunications lasers, the production of the first 1 MB DRAM, the development of semiconductor diagnostic methods, and the pioneering of silicon microphotonics. His MIT research on silicon processing has addressed areas including integrated circuit fabrication, microphotonic materials and devices, solar energy conversion, and environmentally benign integrated circuit manufacturing. Professor Kimerling earned a BS in metallurgy in 1965 and a PhD in 1968, both from MIT. He was head of the Materials Physics Research Department at AT&T Bell Laboratories before joining the MIT faculty in 1990. He is the founding director of the MIT Microphotonics Center and served as director of the MIT Materials Processing Center for 15 years, establishing it as an industry portal for faculty across materials-related disciplines. He leads MIT’s Initiative for Knowledge and Innovation in Manufacturing and is the AIM Photonics Institute executive for education and workforce development. With over 600 technical articles and more than 75 patents in integrated photonics and semiconductor processing, Professor Kimerling is recognized as a leading figure in his field. He is a fellow of numerous professional organizations, including the Minerals, Metals & Materials Society, the Materials Research Society, the American Physical Society, the American Association for the Advancement of Science, and Optica.

Research topics

• Computer Science
• Materials science
• Optoelectronics
• Optics
• Telecommunications
• Engineering
• Physics
• Software engineering
• Embedded system
• Systems engineering
• Electronic engineering
• Crystallography
• Nanotechnology
• Composite material
• Chemistry
• Electrical engineering
• Mechanical engineering

Selected publications

• Advances in waveguide to waveguide couplers for 3D integrated photonic packaging

  Light Science & Applications · 2026-01-01 · 3 citations

  articleOpen access

  In this paper, we provide an overview and comparison of devices used for optical waveguide-to-waveguide coupling including inter-chip edge couplers, grating couplers, free form couplers, evanescent couplers, cantilever couplers, and optical wirebonds. In addition, technology for efficient transmission of light through chips is discussed including guided mode and free form photonic vias for substrates including silicon, glass, and organics. The results are discussed in the context of potential applications including co-packaged optics switch packages, replaceable biochemical sensors, optically connected memory, optical computing, integrated quantum photonics, and integrated LiDAR systems to show possible improvements in energy efficiency, performance, and cost.

  PublisherDOI

• Graded index couplers for next generation chip-to-chip and fiber-to-chip photonic packaging

  Journal of Physics Photonics · 2025-10-22

  articleOpen access

  Abstract The transition towards designs which co-package electronic and photonic die together in data center switch packages has created a scaling path to Petabyte per second (Pbps) input/output (I/O) in such systems. In a co-packaged design, the scaling of bandwidth, cost, and energy will be governed by the number of optical I/O channels and the data rate per channel. While optical communication provide an opportunity to exploit wavelength division multiplexing to scale data rate, the limited 127 µ m pitch of V-groove based single mode fiber arrays and the use of active alignment and bonding for their packaging present challenges to scaling the number of optical channels. Flip-chip optical couplers which allow for low loss, broadband operation and automated passive assembly represent a solution for continued scaling. In this paper, we propose a novel scheme to vertically couple between silicon based waveguides on separate chips using graded index couplers in combination with an evanescent coupler. Simulation results using a 3D finite-difference time-domain solver are presented, demonstrating coupling losses as low as 0.35 dB for a chip-to-chip gap of 11 µ m; 1 dB vertical and lateral alignment tolerances of approximately 2.45 µ m and ± 2.66 µ m, respectively; and a possible 1 dB bandwidth of greater than 1500 nm. These results demonstrate the potential of our coupler as a universal interface in future co-packaged optics systems.

  PublisherDOI

• Fabrication and Passive Assembly of Broadband Evanescent Couplers for Sustainable Pbps Co-Packaged Optics

  IMAPSource Proceedings · 2025-02-13

  articleOpen access

  A passively assembled chip-to-package substrate evanescent coupler between silicon nitride and silicon was experimentally demonstrated across the 1480-1640 nm wavelength regime with a 0.39 ± 1.06 dB coupling loss at 1550 nm, a 160 nm 1-dB wavelength tolerance (1480-1640 nm), and a 1-dB lateral alignment tolerance of ± 1.56 𝜇𝜇m. The thermal stability was evaluated from 23-60°C with average coupling loss and alignment tolerance varying by less than ± 0.35 dB and ± 30 nm, respectively. The repeatability of the packaging process flow was also evaluated by measuring coupler performance across four separately packaged systems, with a total range of 1.5 dB for coupling loss observed. Results show the viability of this coupler to help achieve Pbps co-packaged optics switch performance by eliminating active fiber-to-chip alignment and scaling down optical input/output pitch at the die level.

  PublisherOA PDFDOI

• VR simulation and digital twin based training for workforce development in integrated photonics

  2025-09-17

  articleSenior author

  As electronic-photonic integration and Co-Packaged Optics drive advanced systems solutions for data centers, AI and quantum computing, smart sensing, and augmented imaging systems, VR simulators and digital twins offer a much-needed just-in-time training, interactive learning tool to support rapid and continuous reskill/upskill of engineers and technicians. Recent advances in VR simulations of integrated photonics devices, and digital twins of CPO packaging tools (fiber attach, die saw, die bonder) will be presented, with results on learner experience within an intensive bootcamp and summer training program, and within online training courses. The VR simulation and digital twin development process will be introduced, and assessment of learners and trainers will describe how design/process engineer and technician or operator training may be enhanced with these visualization tools, coupled with a game-based learning methodology to structure self-paced training. Specifically, unique learning affordances in expanding learner perception across multiple spectral ranges, size and time scales, and operation speeds will be examined. Results will also be presented for a digital game that trains in Life Cycle Thinking for resource-efficient manufacturing. This photonics education frontier emphasizes a broader training in semiconductor manufacturing supply chain environmental impact, as a new technology context for integrated photonics systems design and manufacture.

  PublisherDOI

• Graded Index Couplers: A Universal Interface for Photonic Integrated Circuit Packaging

  2025-01-01 · 1 citations

  article

  A silicon oxynitride graded index coupler was designed to connect silicon nitride waveguides on separate chips, demonstrating a simulated coupling loss of 0.45 dB and a 1-dB alignment tolerance of ± 2.3 µ m at 1550 nm for an 11 µ m vertical chip-to-chip gap.

  PublisherDOI

• Fabrication and Packaging of Edge Coupled Silicon Nitride Photonic Integrated Circuits on Glass Substrates for High Performance Interposers

  IMAPSource Proceedings · 2025-11-10

  articleOpen access

  Silicon nitride photonic integrated circuits were fabricated on glass substrates for the first time using reactive ion etched edge facets, demonstrating a minimum propagation loss of 2.4 ± 0.36 dB/cm and minimum edge coupling loss of 2.17 ± 0.79 dB. Two sets of processes were developed: one including high temperature steps (T > 350°C) common to complimentary-metal-oxide-semiconductor (CMOS) foundry front-end-of-line tools and one including low temperature steps (T < 350°C) compatible with CMOS foundry back-end-of-line tools. For both the high and low temperature samples, a CMOS foundry compatible process was also established for dry etching edge facets > 85 𝜇m deep into SiO2 substrates using magnetically enhanced reactive ion etching with amorphous silicon hard masks without metal. Results show the viability of this glass interposer to help achieve Pbps co-packaged optics switch performance by addressing the material limitations of organic or silicon based interposers and enabling pick-and-place assembly of photonic die to package level integrated photonic waveguides.

  PublisherOA PDFDOI

• Low Loss Chip-to-Chip Couplers for Flip-Chip Assembly of Photonic Die in Co-Packaged Optics

  2025-01-01

  article

  A chip-to-chip coupler between silicon nitride and silicon was experimentally demonstrated between 1480-1640 nm with an average coupling loss of 0.73 ± 0.92 dB and an average 1-dB alignment tolerance of 1.38 ± 0.24 µ m. The coupler also showed less than a ± 0.35 dB change for temperatures from 23-60° C and a 1.5 dB range across four packages.

  PublisherDOI

• Digital Twin and Digital Game-Based Training in Integrated Photonics and Semiconductor Resource-Efficiency

  2025-05-19 · 1 citations

  articleSenior author

  As Co-Packaged Optics drives advanced packaging solutions for data centers, AI computing, and sensing/imaging systems, digital twins and digital games offer just-in-time training support for rapid reskill/upskill of engineers and technicians. Recent advances in digital twins of select packaging tools for CPO (fiber-attach, die saw, die bonder) will be presented with early results on learner experience within a bootcamp based setting. In addition, learner results will be presented for a digital game that trains in Life Cycle Thinking for resource-efficient manufacturing. This new photonics education frontier expands CPO curricula to emphasize broad training in the resource flows of the semiconductor manufacturing supply chain, to assess enabling integrated photonics solutions for systems, and in fabrication or packaging.

  PublisherDOI

• Low Loss Chip‐to‐Chip Couplers for High‐Density Co‐Packaged Optics

  Advanced Engineering Materials · 2025-02-01

  articleOpen access

  Co-Packaged Optics In article number 2402095, Drew Weninger, Samuel Serna, and co-workers present a co-packaged optics system with an electrical chip (black, center) surrounded by 8 silicon photonic chips. Chips are bonded using an automated pick-and-place tool, shown placing the final chip into position. The automation is enabled by a novel optical chip-to-chip coupler (green callout).

  PublisherOA PDFDOI

• Graded Index Couplers for Next Generation Chip-to-Chip and Fiber-to-Chip Photonic Packaging

  ArXiv.org · 2025-02-28 · 1 citations

  preprintOpen access

  The transition towards designs which co-package electronic and photonic die together in data center switch packages has created a scaling path to Petabyte per second (Pbps) input/output (I/O) in such systems. In a co-packaged design, the scaling of bandwidth, cost, and energy will be governed by the number of optical I/O channels and the data rate per channel. While optical communication provide an opportunity to exploit wavelength division multiplexing (WDM) to scale data rate, the limited 127 $μ$m pitch of V-groove based single mode fiber arrays and the use of active alignment and bonding for their packaging present challenges to scaling the number of optical channels. Flip-chip optical couplers which allow for low loss, broadband operation and automated passive assembly represent a solution for continued scaling. In this paper, we propose a novel scheme to vertically couple between silicon based waveguides on separate chips using graded index (GRIN) couplers in combination with an evanescent coupler. Simulation results using a 3D Finite-Difference Time-Domain (FDTD) solver are presented, demonstrating coupling losses below 0.27 dB for a chip-to-chip gap of 11 $μ$m; 1-dB vertical and lateral alignment tolerances of approximately 2.38 $μ$m and $\pm$ 2.24 $μ$m, respectively; and a greater than 360 nm 1-dB bandwidth. These results demonstrate the potential of our coupler as a universal interface in future co-packaged optics systems.

  PublisherOA PDFDOI

Frequent coauthors

• Anu Agarwal

  336 shared

• Jürgen Michel

  Massachusetts Institute of Technology

  323 shared

• Juejun Hu

  180 shared

• Vivek Singh

  L V Prasad Eye Institute

  121 shared

• Kathleen Richardson

  106 shared

• Dawn T. H. Tan

  96 shared

• Pao Tai Lin

  Texas A&M University

  89 shared

• Zhengli Han

  Hebrew University of Jerusalem

  71 shared

Labs

• Electronic Materials Research GroupPI

Education

• Ph.D., Materials Science and Engineering

  Massachusetts Institute of Technology

  1990

• M.S., Materials Science and Engineering

  Massachusetts Institute of Technology

  1986

• B.S., Materials Science and Engineering

  Massachusetts Institute of Technology

  1984

Awards & honors

• John Bardeen Award, The Minerals, Metals & Materials Society…
• Frank E. Perkins Award for Excellence in Graduate Advising,…
• Electronics Division Award, The Electrochemical Society (199…
• Humboldt Research Award, Alexander von Humboldt Foundation (…