Kevin Skadron
University of Virginia · Computer Science
Active 1998–2026
Academic metrics are sourced from OpenAlex and public funding records; values may differ from Google Scholar.
About
Kevin Skadron is the Harry Douglas Forsyth Professor of Computer Science at the University of Virginia, where he has been a faculty member since 1999. He holds a B.S. in Electrical and Computer Engineering and a B.A. in Economics from Rice University, obtained in 1994, and a Ph.D. in Computer Science from Princeton University, earned in 1999. His research interests encompass computer architecture, memory architecture and processing in and near memory (Processing-In-Memory/Processing-Near-Memory), automata processing and pattern matching, design verification, and related fields. Throughout his career, Skadron has contributed significantly to the field of computer architecture, serving as department chair from 2012 to 2021 and helping to establish research centers such as the SRC JUMP 1.0 Center for Research on Intelligent Storage and Processing in Memory (CRISP) and the Center for Automata Processing (CAP). He is currently a member of the SRC JUMP 2.0 Center for Research on Processing in Storage and Memory (PRISM). His professional achievements include receiving the 2023 SRC/SIA University Research Award, the 2011 ACM SIGARCH Maurice Wilkes Award, and being named a Fellow of the IEEE and ACM. Skadron has also been recognized as a University of Virginia Teaching Fellow and has held editorial roles in prominent journals and conferences, including co-founding IEEE Computer Architecture Letters and serving as its editor-in-chief. His extensive research portfolio features numerous…
Research topics
- Computer Science
- Parallel computing
- Embedded system
- Operating system
- Programming language
- Computer hardware
- Computer network
- Theoretical computer science
- Computer architecture
- Distributed computing
Selected publications
Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching
2020 · 41 citations
Senior authorCorrespondingHigh-throughput and concurrent processing of thousands of patterns on each byte of an input stream is critical for many applications with real-time processing needs, such as network intrusion detection, spam filters, virus scanners, and many more. The demand for accelerated pattern matching has motivated several recent in-memory accelerator architectures for automata processing, which is an efficient computation model for pattern matching. Our key observations are: (1) all these architectures ar…
2020 · 38 citations
Senior authorCorrespondingIn-situ approaches process data very close to the memory cells, in the row buffer of each subarray. This minimizes data movement costs and affords parallelism across subarrays. However, current in-situ approaches are limited to only row-wide bitwise (or few-bit) operations applied uniformly across the row buffer. They impose a significant overhead of multiple row activations for emulating 32-bit addition and multiplications using bitwise operations and cannot support operations with data depende…
Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAs
2020 · 29 citations
Senior authorCorrespondingRegular expressions have been widely used in various application domains such as network security, machine learning, and natural language processing. Increasing demand for accelerated regular expressions, or equivalently finite automata, has motivated many efforts in designing FPGA accelerators. However, there is no framework that is publicly available, comprehensive, parameterizable, general, full-stack, and easy-touse, all in one, for design space exploration for a wide range of growing patter…
Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching
2021 · 26 citations
The rapid influx of biosequence data, coupled with the stagnation of the processing power of modern computing systems, highlights the critical need for exploring high-performance accelerators that can meet the ever-increasing throughput demands of modern bioinformatics applications. This work argues that processing in memory (PIM) is an effective solution to enhance the performance of k-mer matching, a critical bottleneck stage in standard bioinformatics pipelines, that is characterized by rando…
Architectural Modeling and Benchmarking for Digital DRAM PIM
2024-09-15 · 7 citations
articleSenior authorProcessing In Memory (PIM) integrates computational logic units directly into the memory architecture, offering significant performance improvements for memory-bound applications such as matrix operations, vector operations, and database applications compared to general-purpose CPUs or GPUs. However, the lack of a standardized benchmark suite and simulation framework poses a challenge in exploring, evaluating, and designing different PIM architectures. This paper addresses this gap by introducin…
Recent grants
XPS:FULL: New Abstractions and Applications for Automata Computing
NSF · $875k · 2016–2020
NSF · $270k · 2011–2016
Physically Aware Computer Architecture
NSF · $162k · 2004–2007
Frequent coauthors
- 361 shared
Amara Amara
Beihang University
- 361 shared
Eduard Alarcon
- 361 shared
Bram Nauta
University of Twente
- 361 shared
Andy Chen Vp
University at Buffalo, State University of New York
- 361 shared
Myung Hoon Sunwoo
Texas A&M University
- 361 shared
Jan Van der Spiegel
University of Pennsylvania
- 361 shared
Dennis Frailey
Southern Methodist University
- 361 shared
Yong Lian
University of Calgary
Education
B.S., Electrical and Computer Engineering and B.A.
UNIVERSITY OF VIRGINIA
Awards & honors
- 2023 SRC/SIA UNIVERSITY RESEARCH AWARD
- 2011 ACM SIGARCH MAURICE WILKES AWARD
- Fellow of the IEEE
- Fellow of the ACM
- UNIVERSITY OF VIRGINIA TEACHING FELLOW (2003-04)
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