About

Kenle Chen is an Associate Professor in the Department of Electrical and Computer Engineering at Northeastern University College of Engineering, joining the faculty in January 2026. His research focuses on AI-driven design, heterogeneous integration, and co-design of spectrum- and energy-efficient wireless systems. He has been recognized with the NSF CAREER award in 2023 for his contributions to the field. His work encompasses the development of advanced RF and microwave components, including high-power magnetic-less fully-directional radio front ends, load-modulated balanced amplifiers, and reconfigurable multi-band power amplifiers. His research aims to improve the efficiency, linearity, and resilience of wireless communication systems, with applications in massive MIMO and other advanced wireless technologies.

Research topics

• Computer Science
• Algorithm
• Parallel computing
• Arithmetic
• Mathematics
• Computer hardware
• Engineering
• Electronic engineering
• Embedded system
• Electrical engineering

Selected publications

• Development of a short version of the perceived social support scale: based on classical test theory and ant colony optimization

  BMC Public Health · 2025-01-20 · 26 citations

  articleOpen access

  BACKGROUND: Despite the relatively small number of items on the Perceived Social Support Scale (PSSS-12), there has been a trend toward simplification of the scale in order to minimize testing time. In this situation, some researchers based on the responses of military spouses in the U.S., has simplified the PSSS-12 to develop the PSSS-M6. This study aimed to develop a short version of the PSSS-12 suitable for the Chinese general population. METHODS: A multi-stage stratified cluster sampling method was employed to collect data from 10,914 residents in 120 cities across the country. After randomly dividing the data into two parts, exploratory analysis and confirmatory analysis were conducted separately. During the exploratory analysis of dataset 1, the scale was simplified using both Classical Test Theory (CTT) and the Ant Colony Optimization (ACO), resulting in one short form for each approach. Additionally, three short forms were obtained by introducing other short forms of the Multidimensional Scale of Perceived Social Support (MSPSS) scale derived from multidimensional item response theory in previous studies. The reliability and discriminant validity of the three short forms were tested. Subsequently, the reliability, validity, model fit and measurement invariance for the two short forms of the MSPSS scale were examined using dataset 2. RESULTS: The 6-item short form developed based on the ACO (PSSS-A6) exhibited the best psychometric properties among all the short forms. Moreover, the 3-item short form composed of items with the highest factor loadings in each dimension also demonstrated good psychometric properties. CONCLUSIONS: In future research, if a short form of the MSPSS scale is needed for measurement purposes, the 3-item short form is suitable for clinical settings, large-scale cross-sectional studies, or longitudinal studies, while the PSSS-A6 is more appropriate for more precise measurements. TRIAL REGISTRATION: This study underwent ethical review (JNUKY-2021-018) by Jinan University.

  PublisherOA PDFDOI

• MRAM-Based Cache and In-Memory Computing

  IEEE Nanotechnology Magazine · 2025-04-14 · 2 citations

  article

  The rapid advancement in semiconductor technology has led to a significant gap between the processing capabilities of CPUs and the access speeds of memory, presenting a formidable challenge known as the “memory wall” in traditional Von Neumannarchitectures. Concurrently, the “power wall” dilemma emerges, characterized by escalated transmission overhead due to rapid data transfer and increased static power consumption from the downsizing of CMOS transistors. Addressing these issues, recent research has centered on more energy-efficient design and utilization of caches, thus giving rise to: first, emerging cache designs introducing ultra-low power non-volatile memory (NVM) techniques, and in-memory computing exploiting direct computation from NVM caches. Among the various non-volatile memory technologies, Magnetic Random Access Memory (MRAM) has emerged as one of the most promising technology owing to its high density/performance, low power consumption, and near-infinite lifetime. Hence, in this paper methodically examines MRAM’s distinct models and array configurations, reviews optimization techniques for its peripheral circuits, and evaluates MRAM-based cache architectures. At the same time, it highlights the latest MRAM-IMC prototypes and their progressive applications.

  PublisherDOI

• Energy Efficient Approximate Computing Framework for DNN Acceleration Using a Probabilistic-Oriented Method

  IEEE Transactions on Emerging Topics in Computing · 2025-01-02 · 2 citations

  article

  Approximate computing (AxC) has recently emerged as a successful approach for optimizing energy consumption in error-tolerant applications, such as deep neural networks (DNNs). The enormous model size and high computation cost of DNNs present significant challenges for deployment in energy-efficient and resource-constrained computing systems. Emerging DNN hardware accelerators based on AxC designs selectively approximate the non-critical segments of computation to address these challenges. However, a systematic and principled approach that incorporates domain knowledge and approximate hardware for optimal approximation is still lacking. In this paper, we propose a probabilistic-oriented AxC (PAxC) framework that provides high energy savings with acceptable quality by considering the overall probability effect of approximation. To achieve aggressive approximate designs, we utilize the minimum likelihood error to determine the AxC synergy profile at both application and circuit levels. This enables effective coordination of the trade-off between energy and accuracy. Compared with a baseline design, the power-delay product (PDP) is significantly reduced by up to 83.66% with an acceptable accuracy reduction. Simulation and a case study of the image process validate the effectiveness of the proposed framework.

  PublisherDOI

• Instant-CIM: An Instant Neural Radiance Field Computing-In-Memory Architecture for Low-Power and Real-Time AR/VR Rendering

  IEEE Transactions on Computers · 2025-12-11

  article

  Novel View Synthesis is a foundational technique for creating immersive Augmented and Virtual Reality (AR/VR) experiences, aiming to generate photorealistic images of a scene from arbitrary camera viewpoints using only a limited set of source images, with Neural Radiance Fields (NeRF) emerging as the state-of-the-art solution. However, real-time NeRF rendering on low-power devices remains challenging due to its memory-intensive hash encoding and compute-intensive Multilayer Perception (MLP). In this work, we propose Instant-CIM, the fully on-chip Computing-in-Memory (CIM) architecture for efficient NeRF rendering. At the algorithm level, Instant-CIM proposes a spatially-adaptive framework that dynamically selects the number of active hash encoding levels per spatial region based on a composite importance score derived from density and gradient. The approach replaces uniform level allocation with a threshold-based strategy that activates finer encoding levels only in regions with high representation complexity. At the hardware level, Instant-CIM proposes an in-situ hash engine that implements in-memory hash query and interpolation through 3D scene grid decomposition and Z-order based mapping schemes. Meanwhile, Instant-CIM proposes a sparse MLP engine that leverages differential-based input complemented by a precision-adjustable skipping mechanism to fully exploit spatial similarities. Comprehensive evaluation across synthetic datasets demonstrates that Instant-CIM achieves 3.0×~4.9× improvement in rendering speed and 8.6×~33× enhancement in energy efficiency compared to state-of-the-art NeRF architecture.

  PublisherDOI

• High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme

  2025-05-25 · 1 citations

  article

  In recent years, the rapid advancement of processor performance has highlighted the increasing inadequacy of memory bandwidth. To mitigate this challenge, the In-memory Computing (IMC) architecture has been proposed. Among various IMC implementations, Spin-Orbit Torque Random Access Memory (SOT-MRAM) stands out as an ideal generic co-processor due to its high density and low leakage current. However, how to efficiently integrate with existing instruction set architectures (ISA) while satisfying the characteristics of the SOT-MRAM IMC hardware poses a challenge. In this work, an instruction-driven in-memory co-processor architecture is proposed. By combining the proposed hardware-software collaborative memory redirection scheme, the SOT-MRAM-based in-memory computing can be merged into the existing computing architecture without disturbing ISA. Further, to satisfy the inter-row operation computation characteristics of SOT-MRAM IMC, a data pre-scheduling scheme oriented to efficient computation is proposed. Experimental results demonstrate a 6.2x speedup and 64% power reduction compared to a CPU-only architecture, and a 28% improvement in acceleration ratio over the state-of-the-art IMC architecture.

  PublisherDOI

• SS-MRAM: A Segment-Based Search Scheme With Configurable Matching for High-Accuracy Hyperdimensional Computing in CAM Applications

  IEEE Transactions on Circuits and Systems I Regular Papers · 2025-06-10

  article

  With the rise of hyperdimensional computing (HDC), content-addressable memories (CAMs) have emerged as an ideal choice for processing high-dimensional data. However, despite the advantages of high parallelism and low latency offered by CAM technology, it fails to address the significant loss of inference accuracy caused by closely matching hamming distances (HD). Emerging analog-based imprecise in-memory computing technologies frequently provide a minimum detectable HD that is insufficient for meeting the requirements of high similarity tasks. This limitation provides opportunities for using digital methods to realize fully exact matching memory computing technology based on magnetic random access memory (MRAM). In this work, a segment search scheme based on STT-MRAM devices and address-matching technology is proposed, which achieves zero loss in inference accuracy. An adaptive amplification structure is initially implemented by integrating the discharge method of latch structures, accompanied by the design of a 14T-2MTJ cell circuit. Through the optimization of the matching step, HD are calculated for each segment of configurable-dimensional vectors, ultimately facilitating the classification ranking of query hypervectors based on a comprehensive array architecture. Experimental results indicate that there is zero loss in inference accuracy when each segment of the dimension is configured to be below 16 bits. At 16 bits, the search power consumption in the worst-case matching scenario is measured at 1.73 fJ/bit, while the loss in inference accuracy does not exceed 0.4%.

  PublisherDOI

• Hierarchical attention fusion of EUS-doppler features for GISTs risk assessment

  Computerized Medical Imaging and Graphics · 2025-07-05

  article
  PublisherDOI

• Label-Efficient Point Cloud Semantic Segmentation: A Holistic Active Learning Approach

  World Scientific Annual Review of Artificial Intelligence · 2024-01-01 · 2 citations

  article

  Deep learning models are the state of the art for semantic segmentation of point clouds, the success of which relies on the availability of large-scale annotated datasets. However, it can be prohibitively costly to prepare such datasets. In this work, we propose a holistic active learning (AL) approach to maximize model performance given limited annotation budgets. We investigate the appropriate sample granularity for active selection under the realistic “click” measurement of annotation cost, and demonstrate that superpoint-based selection allows for most efficient usage of the limited budget, when compared with point-level, polygon-level and instance/shape-level selection. We further propose new objective for AL acquisition function and exploit local consistency constraints to boost the performance of our superpoint-based approach. We evaluate our methods on three benchmark datasets, ShapeNet and PartNet and S3DIS. The results demonstrate that AL is an effective strategy to address the high annotation costs in semantic point cloud segmentation.

  PublisherDOI

• Progressive Approximation-Aware Training with Regularization and Transfer Learning for DNN Acceleration

  2024-07-16

  preprintOpen access

  This study introduces a novel progressive approximation-aware training (AAT), which efficiently integrates regularization and transfer learning techniques. The primary objective is to capture the inherent characteristics of approximate hardware designs. By considering the accuracy requirements and computational constraints inherent in the application optimizer, AAT strives to achieve an optimal balance between accuracy and power consumption. Initiating with a quantified deep neural network (DNN) model, AAT employs a range of approximation strategies to pinpoint the optimal model space and minimize energy cost. When compared to cutting-edge techniques, our approach provides remarkable energy savings, enhanced resilience against adversarial attacks, and maintains consistent accuracy.

  PublisherOA PDFDOI

• A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM

  IEEE Transactions on Circuits and Systems I Regular Papers · 2024-05-14 · 6 citations

  article

  Due to the physical separation of data processing and storage, the conventional Von Neumann architecture exists excessive data migration overhead to curtail the progress of data-intensive applications. In this way, the Computing-in-Memory (CiM) architecture is proposed. Due to the boolean property of the memory cell, the current CiM mainly focuses on single-bit logic design. For the multi-bit arithmetic design, a prevalent patchwork approach is employed using single-bit logic, leaving the design with insufficient parallelism. This paper proposes a high-performance in-memory multi-bit addition (M-Add) and multiplication (M-Mul) scheme based on unipolar switching SOT-MRAM. For the M-Add scheme, transmission logic-based circuit design is proposed to realize single-step inter-column XOR operations, which is logically fits perfectly the g operator of parallel prefix algorithm. Further, the oBK algorithm is presented to maximize the g operator occupancy. For the M-Mul scheme, mapping the Booth decoder to the control signal of the proposed modified flip-flop queue, only two steps are required to realize the decoding of three encoded signals in parallel. The simulation results indicate the proposed design reduces the latency of N-bit Add (N-bit Mul) by an average of 82.6% (31.5%) compared to state-of-the-art CiM designs. Further, a CNN application based on proposed operations achieves 1.23 TOPS/w on the CIFAR-10 dataset, with an average of 47.57% increase over other CiM designs.

  PublisherDOI

Frequent coauthors

• Weiqiang Liu

  54 shared

• Bi Wu

  Ministry of Industry and Information Technology

  44 shared

• Chenggang Yan

  Hangzhou Dianzi University

  24 shared

• Tianyang Yu

  23 shared

• Fabrizio Lombardi

  Northeastern University

  20 shared

• Haonan Zhu

  Shaoxing University

  17 shared

• Gong Zhang

  Nanjing University of Aeronautics and Astronautics

  7 shared

• Jie Han

  University of Alberta

  7 shared

Awards & honors

• 2023 NSF CAREER award