About

Kaustav Banerjee is a Professor in the Department of Electrical and Computer Engineering at UC Santa Barbara. His research interests include nanoelectronics, physics, technology, and applications of low-dimensional nanomaterials, as well as 2D materials and their heterostructures. He also focuses on bioelectronics, quantum electronics, and the development of ultra-low power devices, circuits, and sensors. His work involves exploring the fundamental properties and technological applications of nanomaterials and low-dimensional systems, contributing to advancements in electronic and bioelectronic devices.

Research topics

• Quantum mechanics
• Engineering
• Physics
• Electrical engineering
• Nanotechnology
• Optoelectronics
• Computer Science
• Materials science
• Mathematics
• Condensed matter physics
• Optics

Selected publications

• CMOS‐Compatible Pressure‐Assisted Solid‐Phase‐Diffusion Technique for Large‐Area Multilayer Graphene Synthesis

  Small · 2025-07-01

  articleSenior authorCorresponding

  Multilayer graphene (MLG) interconnects, enabled by subtractive etching and intercalation doping, have emerged as a promising solution for advanced Complementary Metal-Oxide-Semiconductor (CMOS) technology nodes, where conventional metal interconnects face escalating challenges, including increased resistance, self-heating, electromigration, and integration complexity. However, traditional MLG synthesis methods typically require high temperatures (>600 °C) and involve transfer from metal catalysts to dielectric substrates-practices incompatible with CMOS back-end-of-line (BEOL) thermal budgets (<500 °C) and prone to introducing defects and wrinkles that hinder wafer-scale integration. To overcome these limitations, this group pioneered a CMOS-compatible, transfer-free growth technique based on pressure-assisted solid-phase diffusion, which enables direct synthesis of high-quality MLG within BEOL constraints. Combined with optimized intercalation doping - originally introduced by this group - this approach achieves significantly enhanced electrical conductivity, exceeding that of sub-30 nm metal wires, with excellent electromigration reliability. This breakthrough has garnered broad attention for its potential to transform interconnect technology and accelerate the integration of graphene into mainstream semiconductor manufacturing. This article presents the scientific rationale, materials physics, and process innovations underpinning this scalable technology, highlighting how catalyst selection, carbon sources, and process parameters govern MLG quality and performance. Beyond interconnects, this work lays a foundation for deploying graphene in optoelectronics, spintronics, photovoltaics, and flexible electronics.

  PublisherDOI

• Exploration and Analysis of Metallic, Optical, and Superconducting Cryo-Interconnects for Large-Scale Quantum Computers

  2024-12-07

  articleSenior author

  Determining optimal interconnect solutions is crucial to realize high-performance and energy-efficient large scale quantum computers (QC). This work presents the first comprehensive exploration and analysis of a wide range of interconnect technologies under cryogenic conditions. We determine the best on-chip interconnect materials for cryogenic interface electronics (CIE) based on required current density and wire geometry among metals, doped-multilayer-graphene (DMLG), as well as superconductors, and, subsequently, evaluate various transistor and interconnect technology combinations for CIE. This is followed by analyzing the heat loads across system-level interconnects (or cables) used to transmit signals across different temperature zones in the dilution refrigerator. Our results indicate that optical-fiber cables are key to realizing large-scale QC beyond 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> qubits.

  PublisherDOI

• Analysis and Implication of Electrothermal Effects in Emerging 3D Transistors and Integration Topologies with Two-Dimensional Semiconductors

  2024-12-07 · 2 citations

  articleSenior author

  This work presents the first comprehensive electrothermal modeling and analysis of two-dimensional semiconductor (2DS) based emerging 3D transistor architectures including nanosheet field-effect transistors (NSFETs) and complementary FETs (CFETs). Using a multi-scale (from materials and interfaces to devices) simulation framework that accurately accounts for the enhanced thermal boundary resistance between 2D layered semiconductors and adjacent materials, our methodology establishes a foundational platform for analyzing the self-heating effect (SHE) and offers comprehensive design guidelines for optimizing the electrothermal and reliability performance of emerging 3D FETs and 3D integration topologies in advanced technology nodes.

  PublisherDOI

• An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs

  Nature Communications · 2024-04-22 · 32 citations

  articleOpen accessSenior author

  Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we reveal the opportunity to significantly improve the energy efficiency of digital neuromorphic hardware by introducing NM circuits employing two-dimensional (2D) transition metal dichalcogenide (TMD) layered channel material-based tunnel-field-effect transistors (TFETs). Our novel leaky-integrate-fire (LIF) based digital NM circuit along with its Hebbian learning circuitry operates at a wide range of supply voltages, frequencies, and activity factors, enabling two orders of magnitude higher energy-efficient computing that is difficult to achieve with conventional material and/or device platforms, specifically the silicon-based 7 nm low-standby-power FinFET technology. Our innovative 2D-TFET based NM circuit paves the way toward brain-like energy-efficient computing that can unleash major transformations in future AI and data analytics platforms.

  PublisherOA PDFDOI

• A Framework for Exploring Gate-Dielectric Materials for High-Performance Two-Dimensional Field-Effect-Transistors

  IEEE Transactions on Materials for Electron Devices · 2024-01-01

  articleSenior author

  The choice and engineering of the gate-dielectric (GD) is of paramount importance to the performance and energy-efficiency of two-dimensional (2D) field-effect-transistors (FETs) that are considered to be primary candidates for sub-10 nm gate length (L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub>) metal-oxide-semiconductor FETs (MOSFETs). Despite remarkable progress achieved in recent years by the semiconductor-industry towards realization of high-performance 2D FETs based on transition-metal dichalcogenides (TMDs), achieving fast switching speeds and low device leakage currents remain an open challenge. More specifically, the effect of traps at the dielectric-2D interface and bulk defects in the dielectric on device performance have not been thoroughly investigated. In this paper, taking a common 2D-TMD material molybdenum disulfide (MoS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>) as an example, we explore various GDs and dielectric-stacks – their interfaces, traps and defects, by using rigorous ab-initio density-functional-theory (DFT) and non-equilibrium-Green's-function (NEGF) transport. Our framework and analysis provide valuable insights into the design of n-type 2D MoS<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs, including their gate leakage (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GL</sub>), subthreshold swing (SS), and ON-current (I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub>), and they can be extended to optimize the design and performance of other 2D FETs. More specifically, we demonstrate that monolayer (1L-) and bilayer (2L-) LaOCl/HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> are promising GD stacks to achieve IRDS required values for I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GL</sub>, SS, and I<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> in n-type 2D FETs. Finally, we develop a framework to derive the design-window in terms of material/interface properties valid for both n-type and p-type 2D FETs and identify potential GD materials as a passivation/seeding layer across different L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> for n-type 2D FETs. The results highlight LaOCl as a promising candidate for L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 7 nm while several materials, including LaOCl and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">h</i>BN, are viable for L<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 10 nm.

  PublisherDOI

• Transistors à effet de champ à capacité négative

  2024-01-01

  book-chapterSenior author

  Le FET à capacité négative est prometteur grâce à la diminution de sa tension d'alimentation. Cependant, l'authenticité de la capacité négative dans différentes conditions d'essai reste controversée. Après l'introduction de ses principes fondamentaux, ce chapitre se concentre sur les défis et opportunités du point de vue de la physique des dispositifs, et présente un aperçu des progrès expérimentaux.

  PublisherDOI

• Strain engineering in 2D FETs: Physics, status, and prospects

  Journal of Applied Physics · 2024-09-06 · 20 citations

  articleOpen accessSenior author

  In this work, we explore the physics and evaluate the merits of strain engineering in two-dimensional van der Waals semiconductor-based FETs (field-effect-transistors) using DFT (density functional theory) to determine the modulation of the channel material properties under strain, and subsequently, their effect on carrier transport properties, i.e., scattering rates, mobility, and then finally simulate and analyze dissipative current transport with a non-equilibrium Green's function–Poisson's equation self-consistent solver. The scattering model includes the effects of charged impurities, intrinsic phonons, and remote phonons as well as the screening effect due to charged carriers. Impact of strain engineering on contact resistance is also incorporated into the transport simulations to determine the potential performance enhancements using strain in practical devices. Based on the comprehensive simulation results, we identify the materials and strain configuration that provide the best improvement in performance. We demonstrate an ON-current gain of 43.3% in a biaxially compressively strained monolayer MoSe2 device achieved through unique valley-crossing. Furthermore, implications of strain engineering for emerging energy-efficient devices based on band-to-band tunneling and spintronics are evaluated to explore uncharted frontiers in beyond-CMOS electron devices.

  PublisherOA PDFDOI

• Three-dimensional transistors with two-dimensional semiconductors for future CMOS scaling

  Nature Electronics · 2024-12-16 · 48 citations

  articleSenior author
  PublisherDOI

• The future transistors

  Nature · 2023 · 540 citations

  Senior authorCorresponding
  • Electrical engineering
  • Engineering
  PublisherDOI

• Negative Capacitance Field‐Effect Transistors

  2023-07-21

  otherSenior author

  Negative-capacitance (NC) field-effect transistors (FETs), as self-explained by the name, employs a negative capacitance in the gate stack to save switching voltage. It is emerging as one of the most promising and widely studied devices, not only due to its supply voltage scalability, but also thanks to its simple structure that involves minimal penalty in added manufacturing complexity. Currently, the fundamentals of NC-FETs, as well as potential challenges and opportunities, have been well established and recognized by the device physicists. The switching of FETs is realized by electrostatic modulation of the potential of the channel through which current is conducted. The chapter depicts all of the relevant capacitors in a generic NC-FET structure. An internal metal gate has been proposed to be inserted between the NC layer and the underlying metal oxide semiconductor field-effect transistors.

  PublisherDOI

Recent grants

• NSF:EAGER: 2D Layered Heterostructure based Tunnel Field-Effect Transistors (TFETs) and Circuits

  NSF · $178k · 2015–2017

• FET:Small: An Integrated Unipolar-0.5T0.5R RRAM Crossbar Array for Neuromorphic Computing

  NSF · $500k · 2021–2024

• SHF:Small: A CAD Framework for Coupled Electrical-Thermal Modeling of Interconnects in 3D Integrated Circuits

  NSF · $450k · 2009–2013

• EAGER: Exploration of 3D-Transistors with 2D-TMDs for Ultimate Miniaturization

  NSF · $250k · 2023–2025

• CPA-DA-T: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications

  NSF · $1.0M · 2008–2013

Frequent coauthors

• Wei Cao

  University of California, Santa Barbara

  62 shared

• Jiahao Kang

  East China University of Technology

  45 shared

• Wei Liu

  Tan Kah Kee Innovation Laboratory

  39 shared

• Chuan Xu

  Wellcome Sanger Institute

  37 shared

• Deblina Sarkar

  Massachusetts Institute of Technology

  35 shared

• R.W. Dutton

  26 shared

• Navin Srivastava

  26 shared

• Santanu Mahapatra

  22 shared

Labs

• Nanoelectronics Research LabPI

  Not provided

Education

• PhD, Electrical Engineering & Computer Sciences

  University of California Berkeley

  1999