Deep Learning to Automate Parameter Extraction and Model Fitting of Two-Dimensional Transistors

Research · 2026-01-01

Flexible radio-frequency carbon nanotube transistors operating at frequencies above 100 GHz

Nature Electronics · 2026-05-12

Synthesis‐Related Nanoscale Defects in Mo‐Based Janus Monolayers Revealed by Cross‐Correlated AFM and TERS Imaging

Small · 2025-08-08 · 4 citations

Abstract 2D Janus transition metal dichalcogenides (TMDs) are promising candidates for various applications including non‐linear optics, energy harvesting, and catalysis. These materials are usually synthesized via chemical conversion of pristine TMDs. Nanometer‐scale characterization of the obtained Janus materials’ morphology and local composition is crucial for both the synthesis optimization and the future device applications. In this work, we present the results of cross‐correlated atomic force microscopy (AFM) and tip‐enhanced Raman spectroscopy (TERS) study of Janus monolayers synthesized by the hydrogen plasma‐assisted chemical conversion of MoSe 2 and MoS 2 . We demonstrate that the choice of both the growth substrate and the starting TMD influences the residual strain, thereby shaping the nanoscale morphology of the resulting Janus material. Furthermore, by employing TERS imaging, we show the presence of nanoscale islands (≈20 nm across) of MoSe 2 ‐ (MoS 2 ‐) vertical heterostructures originating from the bilayer nanoislands in the precursor monolayer crystals. The understanding of the origins of nanoscale defects in Janus TMDs revealed in this study can help with further optimization of the Janus conversion process towards uniform and wrinkle‐/crack‐free Janus materials. Moreover, this work shows that cross‐correlated AFM and TERS imaging is a powerful and accessible method for studying nanoscale composition and defects in Janus TMD monolayers.

Gate Dielectric Engineering with an Ultrathin Silicon-oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

ArXiv.org · 2025-11-02

We demonstrate a gate dielectric engineering approach leveraging an ultrathin, atomic layer deposited (ALD) silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V$_T$) of AOS transistors, providing at least four distinct $V_T$ levels with a maximum increase of 500 mV. It achieves stable $V_T$ control without significantly degrading critical device parameters such as mobility, on-state current, all while keeping the process temperature below 225 $^{\circ}$C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 $^{\circ}$C indicate a significant reduction in negative $V_{T}$ shifts for SiL-integrated devices, highlighting enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage ($V_{SN}$) (reduces $V_{SN}$ drop by 67\%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10,000 s at room temperature and reduce standby leakage current by three orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

Key to Low Supply Voltage: Transition Region of Oxide Semiconductor Transistors

2025-06-08 · 6 citations

We study the voltage transition region (TR) from sub- to above-threshold of field-effect transistors (FETs) and characterize its width (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TR}}$</tex>) which informs how much the supply voltage (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{DD}}$</tex>) can be reduced. The TR is significant in amorphous oxide semiconductor field-effect transistors (OSFETs) because the shallow traps in amorphous OS channels lead to large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex>. We introduce a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex> extraction scheme and identify four main sources of shallow traps (ST) in amorphous OSFETs. We design experiments to individually evaluate their impact on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex> and successfully devise four OSFET process/design knobs to minimize V TR. Our analysis is then extended to other prominent FETs in the literature, with crystalline channel FETs showing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TR}}&lt;80 \text{mV}$</tex>, in contrast to amorphous OSFETs with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text {TR }}$</tex> ranging from 160 mV to as high as 1.1 V, highlighting that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{TR}}$</tex> in amorphous OSFETs is a critical challenge that must be addressed.

Monte Carlo Simulation of Electrical Transport with Joule Heating and Strain in Monolayer MoS₂ Devices

Nano Letters · 2025-04-16 · 5 citations

Two-dimensional (2D) semiconductors are candidates for future nanoscale (e.g., nanosheet) transistors, wherein high current densities and high-density integration cause self-heating, limiting performance and reliability. Here, we study the effects of self-heating and strain on electrical transport in monolayer MoS2 using electro-thermal Monte Carlo simulations. Incorporating Joule self-heating with a generalizable thermal resistance model reveals that at high lateral field (∼5 V/μm) and high charge carrier density (∼1013 cm–2), transistor temperatures can increase by more than 200 K in steady state. The electron saturation velocity decreases to 2.1 × 106 cm/s with self-heating but can reach 5.3 × 106 cm/s at room temperature if self-heating is mitigated and tensile strain is applied to reduce intervalley scattering. Simulations also reveal that electron mean free paths are just 2–3 nm in this high-field regime. These results provide fundamental insights showing that both self-heating and strain must be considered in emerging 2D transistors.

Direct ALD of amorphous MoS2 thin films for extra-terrestrial photovoltaic applications

2025-06-08

The design of solar cells for space applications demands a high power-to-weight ratio and resilience against extreme environments, including proton radiation and rapid temperature fluctuations. However, existing technologies come with drawbacks: III-V materials are expensive, CdTe and CIGS rely on scarce and toxic elements, perovskites suffer from stability issues, and silicon has limited limited tolerance to space-stressors. This study investigates ultra-thin amorphous MoS2 as a viable alternative, offering a balance of affordability, environmental sustainability, and robustness. Using atomic layer deposition (ALD), we enable scalable production of photovoltaic-grade amorphous MoS2 thin films, achieving large-area coatings with exceptional uniformity, smoothness, and precise thickness control. Passivation increases the charge carrier lifetime to approximately 100 ns, highlighting the potential for high specific power in a fully encapsulated module. Additionally, unpassivated films show minimal disorder when exposed to high-energy, high-fluence proton radiation. These results highlight the promise of amorphous MoS2 for space-based photovoltaics and lay the groundwork for further studies on its long-term durability in extraterrestrial conditions.

An electro-optical Mott neuron based on niobium dioxide

Nature Electronics · 2025-07-28 · 8 citations

Efficiency Limit of Transition Metal Dichalcogenide-Silicon Tandem Solar Cells

2025-06-08 · 1 citations

Interface-Driven Performance and Thermal Effects in Dual-Gated ITO Transistors

2025-06-22

Amorphous oxide semiconductors like indium tin oxide (ITO) are promising for field-effect transistors (FETs) with high drive currents and low off-state currents [1–5], enabling back-end-of-line ($\leq 500^{\circ} \mathrm{C}$) [6] integration due to their ability to be deposited at low temperatures on a large scale [1–5, 7, 8]. However, fabricating nanoscale ITO transistors with dual gate control remains challenging, as the device performance is highly susceptible to the interfaces with the top-gate dielectric and the metal contacts [9]. While we have previously demonstrated dual-gated ITO transistors with high current [10], the physical mechanisms behind degradation at short ($\lt 100 \mathrm{~nm}$) channel lengths were not explored. Moreover, the thermal implications of high drive currents in oxide transistors also remain unknown. Here, we address these research gaps to provide physical insights and highlight key parameters for future designs.