About

David Kebo Houngninou is an Instructional Associate Professor in the Department of Computer Science & Engineering at Texas A&M University. He holds a Ph.D. in Computer Engineering from Southern Methodist University, obtained in 2017, a Master's degree in Computer Engineering from Washington University in St. Louis earned in 2010, and a Bachelor's degree in Computer Engineering from the University of Evansville completed in 2008. His research interests include logic synthesis, hardware formal verification and validation, and Boolean/switching theory. Houngninou has been recognized with awards such as the Research Days Outstanding Poster Award and the Outstanding Graduate Student Award at Southern Methodist University. His work involves the simulation and implementation of switching circuits using transfer functions, contributing to the field of circuit modeling and verification.

Research topics

• Computer Science
• Programming language
• Software engineering
• Computer architecture
• Operating system
• Multimedia
• World Wide Web
• Pedagogy
• Mathematics education

Selected publications

• BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis

  2025-09-08 · 1 citations

  articleSenior author

  Hardware complexity continues to strain verification resources, motivating the adoption of machine learning (ML) methods to improve debug efficiency. However, ML-assisted debugging critically depends on diverse and scalable bug datasets, which existing manual or automated bug insertion methods fail to reliably produce. We introduce BugGen, a first of its kind, fully autonomous, multi-agent pipeline leveraging Large Language Models (LLMs) to systematically generate, insert, and validate realistic functional bugs in RTL. BugGen partitions modules, selects mutation targets via a closed-loop agentic architecture, and employs iterative refinement and rollback mechanisms to ensure syntactic correctness and functional detectability. Evaluated across five OpenTitan IP blocks, BugGen produced 500 unique bugs with 94% functional accuracy and achieved a throughput of 17.7 validated bugs per hour—over five times faster than typical manual expert insertion. Additionally, BugGen identified 104 previously undetected bugs in OpenTitan regressions, highlighting its utility in exposing verification coverage gaps. Compared against Certitude, BugGen demonstrated over twice the syntactic accuracy, deeper exposure of testbench blind spots, and more functionally meaningful and complex bug scenarios. Furthermore, when these BugGen-Generated datasets were employed to train ML-based failure triage models, we achieved high classification accuracy (88.1%–93.2%) across different IP blocks, confirming the practical utility and realism of generated bugs. BugGen thus provides a scalable solution for generating high-quality bug datasets, significantly enhancing verification efficiency and ML-assisted debugging.

  PublisherDOI

• Improving Last-Mile Coverage in Functional Verification

  2025-09-08

  article

  Functional coverage closure, particularly for the challenging "last-mile coverage" (LMC) bins in complex RTL designs, remains a critical verification bottleneck. Prevailing approaches often require intrusive testbench modifications, introducing instability into mature verification setups. We propose a non-intrusive automated framework that accelerates LMC closure by intelligently adjusting existing high-level testbench knobs. First, static analysis using Abstract Syntax Tree (AST) parsing and Cone-of-Influence (COI) tracing identifies testbench knobs most relevant to specific LMC targets. Next, we employ a conditional generative adversarial network (cGAN) guided by this analysis to generate effective knob configurations. A novel surrogate evaluator within the cGAN, trained on historical simulation data and coverage-proximity metrics, predicts which configurations are likely to hit previously uncovered bins, circumventing the lack of direct positive examples. Experiments on OpenTitan AES and Entropy Source IP blocks demonstrate that our framework successfully closes an additional 2% of difficult LMC bins unresolved by heuristic methods. Further, downstream ML-based failure triage models trained using our generated datasets achieve high classification accuracy, confirming the realism and practical utility of these generated scenarios. Our approach advances automated coverage closure while preserving testbench integrity and significantly reducing manual intervention.

  PublisherDOI

• BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis

  ArXiv.org · 2025-06-12

  preprintOpen accessSenior author

  Hardware complexity continues to strain verification resources, motivating the adoption of machine learning (ML) methods to improve debug efficiency. However, ML-assisted debugging critically depends on diverse and scalable bug datasets, which existing manual or automated bug insertion methods fail to reliably produce. We introduce BugGen, a first of its kind, fully autonomous, multi-agent pipeline leveraging Large Language Models (LLMs) to systematically generate, insert, and validate realistic functional bugs in RTL. BugGen partitions modules, selects mutation targets via a closed-loop agentic architecture, and employs iterative refinement and rollback mechanisms to ensure syntactic correctness and functional detectability. Evaluated across five OpenTitan IP blocks, BugGen produced 500 unique bugs with 94% functional accuracy and achieved a throughput of 17.7 validated bugs per hour-over five times faster than typical manual expert insertion. Additionally, BugGen identified 104 previously undetected bugs in OpenTitan regressions, highlighting its utility in exposing verification coverage gaps. Compared against Certitude, BugGen demonstrated over twice the syntactic accuracy, deeper exposure of testbench blind spots, and more functionally meaningful and complex bug scenarios. Furthermore, when these BugGen-generated datasets were employed to train ML-based failure triage models, we achieved high classification accuracy (88.1%-93.2%) across different IP blocks, confirming the practical utility and realism of generated bugs. BugGen thus provides a scalable solution for generating high-quality bug datasets, significantly enhancing verification efficiency and ML-assisted debugging.

  PublisherOA PDFDOI

• Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization

  ArXiv.org · 2025-05-12

  preprintOpen access

  SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, labor-intensive, and error-prone process. Recent advances in automatic assertion generation, particularly those using machine learning and large language models (LLMs), have shown promising potential, though most approaches remain in the early stages of development. In this work, we introduce Spec2Assertion, a new technique for automatically generating assertions from design specifications prior to RTL implementation. It leverages LLMs with progressive regularization and incorporates Chain-of-Thought (CoT) prompting to guide assertion synthesis. Additionally, we propose a new evaluation methodology that assesses assertion quality across a broad range of scenarios. Experiments on multiple benchmark designs show that Spec2Assertion generates 70% more syntax-correct assertions with 2X quality improvement on average compared to a recent state-of-the-art approach.

  PublisherOA PDFDOI

• FLIP: A RISC-V Visual Computer Architecture Simulator for K-12

  2022

  1st authorCorresponding
  • Computer Science
  • Computer Science
  • Computer architecture

  Computer science and engineering students in college get introduced to high-level language programming (Java, C++, Python) early in their first year and later to computer organization and architecture courses. Most students lack a clear understanding of the architecture of a computer before learning how to write code for the first time. This deficiency is due to the lack of courses focused on computer architecture and organization early in high school. Even though introductory computer science courses are now offered from 6th to 12th grade, in some schools, the curriculum lacks emphasis on the fundamentals of computer architecture. Students interested in computer science should be capable of building a simple processor to better understand the design principles of a computer. We are developing a simulator that allows students to build a custom RISC-V processor and run programs on it. The increasing interest in the RISC-V ISA, and its fast adoption for chip design, make this instruction set a great candidate for this educational tool.

  PublisherDOI

• Early Introduction to Computer Architecture in K-12

  2022 · 1 citations

  1st authorCorresponding
  • Computer Science
  • Computer Science
  • Software engineering

  Computer science and engineering students in college get introduced to high-level language programming (Java, C++, Python) early in their first year and later to computer organization and architecture courses. Most students lack a clear understanding of the architecture of a computer before learning how to write code for the first time. This deficiency is due to the lack of courses focused on computer architecture and organization early in high school. Even though introductory computer science courses are now offered from 6th to 12th grade, in some schools, the curriculum lacks emphasis on the fundamentals of computer architecture. This work presents an educational framework suitable for K-12 and undergraduate college students to learn computer architecture by building custom processors, exploring computer subsystems, and observing how programs are simulated in real-time.

  PublisherOA PDFDOI

• Simulation of switching circuits using transfer functions

  2017-08-01 · 3 citations

  article1st authorCorresponding

  Simulation of complex hardware circuits is the basis for many EDA tasks and is commonly used at various phases of the design flow. State-of-the-art simulation tools are based upon discrete event simulation algorithms and are highly optimized and mature. Symbolic simulation may also be implemented using a discrete event approach, or other approaches based on extracted functional models. The common foundation behind modern simulation tools is that of a switching or Boolean algebraic model that may be augmented with timing information. Recently, an alternative foundational model for conventional digital electronic circuits has been proposed, based upon linear algebra rather than Boolean switching algebra where the circuits are modeled as transfer functions in the form of linear transformation matrices. We demonstrate that this model can be effectively used as the basis for a simulation methodology. Our approach is motivated by the need to develop a truly unified EDA tool for mixed signal circuit design. Currently, industrial tools such as SPECTRE use two different internal engines; a SPICE-like engine and a Verilog-like engine. Our method will allow us to represent mixed signal circuit elements as transfer functions. Spatial complexity is significantly reduced through the use of binary decision diagrams (BDD) to represent the transfer functions. A prototype implementation is used to generate experimental results and to illustrate the viability of the linear algebraic model as a basis for EDA applications.

  PublisherDOI

• Implementation of Switching Circuit Models as Vector Space Transformations

  SMU Scholar (Southern Methodist University) · 2017-01-01

  articleOpen access1st authorCorresponding

  Modeling of switching circuits is the foundation for many Electronic Design Automation (EDA) tasks and is commonly used at various phases of the design flow for tasks such as simulation, justification, and other analyses. State-of-the-art simulation tools are based on discrete event algorithms using switching algebraic models and are highly optimized and mature. Symbolic simulation may also be implemented using a discrete event approach, or other approaches based on extracted functional models. The common foundation of modern simulation tools is that of a switching or Boolean algebraic model that may be augmented with timing information. Justification using switching circuit models are often based on solving the satisfiability problem and can be computationally expensive. Alternative models, such as the one proposed here have the potential to allow for advances in performance and storage requirements in applications such as simulation and justification. Recently, an alternative foundational model for conventional digital electronic circuits has been proposed where the circuits are modeled as transfer functions in the form of matrices. The essence of the new model is to represent information as an element in a vector space rather than as a switching function variable. In this way, switching circuits are likewise modeled as transformations from one vector space to another. We demonstrate that the vector space model can be effectively used as the basis for symbolic simulation, justification, and other applications. A central issue in using the vector space model is that representations and manipulations of the models must not incur complexity any worse than that of algorithms based upon traditional switching algebraic approaches. In particular, we show that Algebraic Decision Diagrams (ADDs) can be used to represent vector space models thus allowing the advantages of the vector space approach to be realized while also ensuring the complexity of the underlying algorithms are no worse than that of conventional switching algebraic models. Spatial complexity is significantly reduced through the use of ADDs to represent the transfer functions as compared to explicit representations and they serve to illustrate the viability of the linear algebraic model in EDA applications. A transfer function is a mathematical function relating the output or response of a system to the input or stimulus. It is a concise mathematical model representing the input/output behavior of a system, and it is widely used in many areas of engineering including system theory and signal analysis. We implement a framework to build transfer function models of digital switching functions using ADDs and demonstrate their application to simulation, justification, and the computation of the algebraic normal form (ANF). Cryptographic primitives may be composed of collections of switching functions. The Algebraic Normal Form (ANF) of a cryptographic switching function is of general interest since this form allows for the computation of many characteristics of interest to the cryptography community. One interesting property of the ANF is that it allows for direct observation of the algebraic degree of a switching function. We present a technique to determine the ANF of switching functions through the traversal of a structural netlist with complexity O(n).

  PublisherDOI

• Implementation of switching circuit models as transfer functions

  2016-05-01 · 4 citations

  article1st authorCorresponding

  A transfer function is a mathematical function relating the output or response of a system to the input or stimulus. It is a concise mathematical model representing the input/output behavior of a system and is widely used in many areas of engineering including system theory and signal analysis. Binary Decision Diagrams (BDDs) are a canonical representation of Boolean functions. We implement a framework to build transfer function models of digital switching functions using BDDs and demonstrate their application on simulation and implication.

  PublisherDOI

Frequent coauthors

• Mitchell A. Thornton

  4 shared

• Maristela Holanda

  Universidade de Brasília

  1 shared

• Dilma Da Silva

  1 shared

Education

• Ph.D. Computer Engineering, Computer Science and Engineering

  Southern Methodist University

  2017

Awards & honors

• Research Days Outstanding Poster Award, Southern Methodist U…
• Outstanding Graduate Student Award, Southern Methodist Unive…